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W3DG72256V-D2
2GB - 256Mx72 SDRAM, REGISTER and SPD, w/PLL
FEATURES
Burst Mode Operation Auto and Self Refresh capability LVTTL compatible inputs and outputs Serial Presence Detect with EEPROM Fully synchronous: All signals are registered on the positive edge of the system clock Programmable Burst Lengths: 1, 2, 4, 8 or Full Page 3.3V 0.3V Power Supply 168 Pin DIMM JEDEC * PCB - D2: 37.34mm (1.47")
DESCRIPTION
The W3DG72256V is a 256Mx72 synchronous DRAM module which consists of eighteen 256Mx4 stack SDRAM components in TSOP II package, two 18 bit Drive ICs for input control signal and one 2Kb EEPROM in an 8 pin TSSOP package for Serial Presence Detect which are mounted on a 168 pin DIMM multilayer FR4 Substrate.
* This product is subject to change without notice. NOTE: Consult factory for availability of: * RoHS compliant products * Vendor source control options * Industrial temperature option
PIN CONFIGURATIONS (FRONT SIDE/BACK SIDE)
PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 FRONT VSS DQ0 DQ1 DQ2 DQ3 VCC DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VCC DQ14 DQ15 CB0 CB1 VSS NC NC VCC WE# DQM0 PIN 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 BACK DQM1 CS0# DNU VSS A0 A2 A4 A6 A8 A10/AP BA1 VCC VCC CK0 VSS DNU CS2# DQM2 DQM3 DNU VCC NC NC CB2 CB3 VSS DQ16 DQ17 PIN 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 FRONT DQ18 DQ19 VCC DQ20 NC *VREF *CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VCC DQ28 DQ29 DQ30 DQ31 VSS *CK2 NC NC **SDA **SCL VCC PIN 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 BACK VSS DQ32 DQ33 DQ34 DQ35 VCC DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VCC DQ46 DQ47 CB4 CB5 VSS NC NC VCC CAS# DQM4 PIN 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 BACK DQM5 CS1# RAS# VSS A1 A3 A5 A7 A9 BA0 A11 VCC *CK1 A12 VSS CKE0 CS3# DQM6 DQM7 *A13 VCC NC NC CB6 CB7 VSS DQ48 DQ49 PIN 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 BACK DQ50 DQ51 VCC DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VCC DQ60 DQ61 DQ62 DQ63 VSS *CK3 NC **SA0 **SA1 **SA2 VCC
PIN NAMES
A0 - A12 BA0-1 DQ0-63 CB0-7 CK0 CKE0 CS0#, CS3# RAS# CAS# WE# DQM0-7 VCC VSS *VREF REGE SDA SCL SA0-2 DNU NC Address Input (Multiplexed) Select Bank Data Input/Output Check Bit (Data-In/Data-Out) Clock Input Clock Enable Input Chip Select Input Row Address Strobe Column Address Strobe Write Enable DQM Power Supply (3.3V) Ground Power Supply for Reference Register Enable Serial Data I/O Serial Clock Address in EEPROM Do Not Use No Connect
* These pins are not used in this module. ** These pins should be NC in the system which does not support SPD.
August 2005 Rev. 3
1
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FUNCTIONAL BLOCK DIAGRAM
CS1# CS0# DQMB0 #
DQ0 DQ1 DQ2 DQ3
W3DG72256V-D2
DQMB4
DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQ32 DQ33 DQ34 DQ35 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQ4 DQ5 DQ6 DQ7
DQ36 DQ37 DQ38 DQ39
DQMB1
DQ8 DQ9 DQ10 DQ11 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQMB5
DQ40 DQ41 DQ42 DQ43 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQ12 DQ13 DQ14 DQ15
DQ44 DQ45 DQ46 DQ47
CB0 CB1 CB2 CB3
CB4 CB5 CB6 CB7
CS2# DQMB2
DQ16 DQ17 DQ18 DQ19 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
CS3# DQMB6
DQ48 DQ49 DQ50 DQ51 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQ20 DQ21 DQ22 DQ23
DQ52 DQ53 DQ54 DQ55
DQMB3
DQ24 DQ25 DQ26 DQ27 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQMB7
DQ56 DQ57 DQ58 DQ59 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3 DQM CS I/O 0 I/O 1 I/O 2 I/O 3
DQ28 DQ29 DQ30 DQ31
DQ60 DQ61 DQ62 DQ63
SERIAL PD CS0#-CS3# DQMB0 to DQMB7 BA0-BA1 A0-A12 RAS# CAS# CKE0 CKE1 WE# REGE PCK R E G I S T E R RS0#-RS3# RDQMB0-RDQMB7 RBA0-RBA1 BA0-BA1: SDRAMS RA0-RA12 A0-A12: SDRAMS RRAS# RAS#: SDRAMS RCAS# CAS#: SDRAMS RCKE0 CKE0: SDRAMS CKE1: SDRAMS RCKE1 RWE# WE#: SDRAMS SCL A0 SA0 VCC VSS A1 SA1 A2 SA2 SDRAMs SDRAMs SDA
* Wire per Clock Loading Table/Wiring Diagrams
NOTE: DQ wiring may differ than described in this drawing, however DQ/DQMB/CKE/S relationships must be maintained as shown.
SDRAM CK0 12pF
PLL
CK1-CK3 REGISTER 12pF
NOTE: All resistor values are 10 ohms.
August 2005 Rev. 3
2
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to VSS Voltage on VCC supply relative to VSS Storage Temperature Power Dissipation Short Circuit Current Symbol VIN, VOUT VCC, VCCQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 36 50
W3DG72256V-D2
Units V V C W mA
Note: Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
RECOMMENDED DC OPERATING CONDITIONS
Voltage Referenced to: VSS = 0V, 0C TA 70
Parameter Supply Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input Leakage Current Symbol VCC VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -- -10 Typ 3.3 3.0 -- -- -- -- Max 3.6 VCCQ+0.3 0.8 -- 0.4 10 Unit V V V V V A 1 2 IOH= -2mA IOL= -2mA 3 Note
Note: 1. VIH (max)= 5.6V AC. The overshoot voltage duration is 3ns. 2. VIL (min)= -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VCCQ Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
TA = 25 C, f = 1MHz, VCC = 3.3V, VREF = 1.4V 200mV
Parameter Input Capacitance (A0-A12) Input Capacitance (RAS#,CAS#,WE#) Input Capacitance (CKE0) Input Capacitance (CLK0) Input Capacitance (CS0#,CS2#) Input Capacitance (DQM0-DQM7) Input Capacitance (BA0-BA1) Data input/output capacitance (DQ0-DQ63) Data input/output capacitance (CB0-CB7)
August 2005 Rev. 3
Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT COUT1
Max 9 9 9 17 9 7 9 16 16
Unit pF pF pF pF pF pF pF pF pF
3
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OPERATING CURRENT CHARACTERISTICS
VCC = 3.3V, 0C TA 70C
Parameters Symbol Conditions
W3DG72256V-D2
Versions 133/100
Units mA
Note 1
Operating Current (One bank active) Precharge Standby Current in Power Down Mode Precharge Standby Current in Non-Power Down Mode
ICC1
Burst Length = 1 tRC tRC(min) IOL = 0mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC =10ns Input signals are charged one time during 20 CKE VIH(min), CLK VIL(max), tCC= Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are charged one time during 20ns CKE VIH(min), CLK VIL(max), tCC = input signals are stable Io = mA Page burst 4 Banks activated tCCD = 2CLK tRC tRC(min) CKE 0.2V
7525
ICC2P ICC2PS ICC2N ICC2NS
541 450 1405 468 468 375 2125
mA mA mA mA mA mA mA
3 3 3 3 3 3 3
Active standby current in power-down mode Active standby in current non powerdown mode
ICC3P ICC3PS ICC3N
ICC3NS Operating current (Burst mode) ICC4
1487 7525
mA mA
3 1
Refresh current Self refresh current
Notes: 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Measured with 1 PLL & 2 Drive ICs.
ICC5 ICC6
12205 577
mA mA
2 3
August 2005 Rev. 3
4
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
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ORDERING INFORMATION FOR D2
Part Number W3DG72256V10D2 W3DG72256V7D2 W3DG72256V75D2 Speed 100MHz 133MHz 133MHz CAS Latency CL=2 CL=2 CL=3
W3DG72256V-D2
Height* 37.34 (1.47") 37.34 (1.47") 37.34 (1.47")
NOTES: * Consult Factory for availability of RoHS compliant products. (G = RoHS Compliant) * Vendor specific part numbers are used to provide memory components source control. The place holder for this is shown as lower case "x" in the part numbers above and is to be replaced with the respective vendors code. Consult factory for qualified sourcing options. (M = Micron, S = Samsung & consult factory for others) * Consult factory for availability of industrial temperature (-40C to 85C) option
PACKAGE DIMENSIONS FOR D2
6.60 (0.260) MAX. 133.35 (5.250) 3.99 (0.157 0.004) (2X) 3.18 (0.125) (2X)
37.34 (1.470) 17.78 (0.700) (0.000) 3.10 (0.122) 8.89 (0.350)
P1
11.43 (0.450) 15.60 (0.614)
36.83 (1.450) 6.35 (0.250)
54.61 (2.150) 6.35 (0.250)
3.99 (0.157) MIN.
57.79 (2.275) 115.57 (4.550) 1.27 0.10 (0.050 .004)
(0.000)
* ALL DIMENSIONS ARE IN MILLIMETERS AND (INCHES)
August 2005 Rev. 3
5
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com
White Electronic Designs
Document Title
2GB- 256Mx72 SDRAM, REGISTER and SPD, w/PLL
W3DG72256V-D2
Revision History Rev #
Rev A Rev B
History
Created Datasheet B.1 Corrected block diagram B.2 Change module height to 1.10"
Release Date
11-6-01 1-22-02
Status
Advanced Advanced
Rev C
C.1 Pg. 5 corrected spec. Pg. 6 corrected module width dimension 2.2 Changed from advanced to preliminary
3-25-02
Advanced
Rev 0 Rev 1 Rev 2
Changed from Advanced to Final Changed mechanical package dimensions 2.1 Updated CAP and IDD Specs 2.2 Removed "ED" from part number
9-19-02 1-22-04 6-1-04
Final Final Final
Rev 3
3.1 Correction to module Height changed from 1.10" to 1.47"
8-05
Final
August 2005 Rev. 3
6
White Electronic Designs Corporation * (602) 437-1520 * www.wedc.com

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